Flash memory is a non-volatile memory that can be electrically programmed (written with data) and electrically erased. Its use has become increasingly popular in consumer and enterprise data storage applications. However, flash memory has an erase/write endurance limit, for example, 10,000 erase/write cycles for multi-level cells, after which the device becomes unreliable. It is not uncommon to encounter this limit in practical applications, so the limit is a significant obstacle for more widespread adoption. In addition, the erase and write operations of conventional flash memory architectures act on large groups of cells, limiting write-access speeds and reducing device lifetimes. For example, solid-state drives (SSDs), can be 10% or less of what might be expected if the architecture allowed each cell to be erased and written individually. Similar architectural limitations apply to a broad class of solid-state non-volatile storage devices including NAND-gate based flash memory (“NAND flash”), NOR-gate based flash memory (“NOR flash”) and phase-change memory.
To reduce the frequency of erase operations, some conventional solid-state drives employ a software module to manage the placement of logical page addresses (seen by a user of the device) into physical page addresses (used by the device). In some conventional architectures, this software module is called the Flash Translation Layer (FTL). The FTL acts to reduce the total number of erase events, and seeks to level wear of cells throughout the device. Writes from device users can be highly non-uniform. For example, “hot” logical page addresses may be re-written at high frequency (e.g., file-system logs) while “cold” logical page addresses may be written only once in the lifetime of the device (e.g. archived photos or documents). Without wear-leveling, the lifetime of the device may be significantly reduced by even modest amounts of hot data. However, conventional wear-leveling can be a costly operation both in terms of excess capacity needed for page relocations, as well as in terms of increased average wear due to copying of static data.
Conventional attempts to enhance the performance of solid-state non-volatile storage devices with respect to speed and/or lifetime are inefficient, ineffective, inflexible and/or have undesirable side effects or other drawbacks with respect to one or more practical applications. For example, some conventional schemes have desirable theoretical properties, but would involve significant, costly and/or impractical changes to conventional device architecture.
Embodiments of the invention are directed toward solving these and other problems individually and collectively.